🎯 Objective

To provide hands-on exposure to RTL Design and Functional Verification methodologies using industry-standard HDL languages and verification environments. Participants will learn how to architect, design, simulate, and verify digital circuits ensuring correctness, reliability, and functional coverage aligned with modern ASIC/SoC flows.

📌 Key Topics Covered

• Module 1: Basics of Digital Design & RTL Concepts
  • Combinational & sequential logic fundamentals
  • RTL design flow and hierarchy
  • Introduction to Verilog/SystemVerilog
• Module 2: RTL Coding & Best Practices
  • RTL coding guidelines for synthesis
  • Blocking vs non-blocking assignments
  • FSM design, datapath & control logic
  • Design constraints and coding for reusability
• Module 3: Verification Fundamentals
  • Verification flow and testbench architecture
  • Simulation basics using EDA tools
  • Assertions and functional coverage concepts
• Module 4: SystemVerilog for Verification
  • SystemVerilog data types, interfaces, OOP concepts
  • Assertions (SVA) and Constrained Random Verification
  • Coverage-driven Verification
• Module 5: UVM (Universal Verification Methodology)
  • UVM components – driver, monitor, agent, scoreboard
  • UVM testbench development
  • Debugging and waveform analysis
• Module 6: RTL Sign-off & Industry Practices
  • Lint checks and CDC (Clock Domain Crossing)
  • Simulation sign-off metrics
  • Best practices for RTL integration into ASIC flow

💻 Hands-on Practical Sessions with Industry Standard Tools

• RTL coding in Verilog/SystemVerilog
• Simulation using leading EDA tools
• Assertion-based verification
• Coverage analysis and debugging
• UVM testbench development & execution

👨‍🎓 Target Audience

• VLSI engineers & professionals
• M.Tech/B.Tech students (ECE, VLSI, Embedded Systems)
• Faculty & researchers in semiconductor domain
• Anyone interested in RTL Design and Functional Verification

📅 Duration & Mode

2–5 days (customizable based on depth)
Mode: Offline / Online (Remote Labs)

📜 Outcomes

• Understand RTL design principles and HDL constructs
• Ability to code synthesizable RTL using Verilog/SystemVerilog
• Develop functional verification testbenches using SystemVerilog and UVM
• Perform lint, CDC checks, simulations, and functional coverage analysis
• Gain hands-on experience with industry verification tools
• Be industry-ready for RTL Design & Verification engineering roles