The Design for Testability (DFT) internship is a comprehensive **12-Week, 100+ Hours** program designed to provide an in-depth, hands-on understanding of test methodologies used in modern chip design. Participants will master the complete DFT flow, from scan insertion and ATPG pattern generation to fault analysis and sign-off, using industry-standard Cadence tools.
Reasons to invest in your VLSI career with us.
Learn from industry veterans with 10+ years of experience at top semiconductor Industries.
80% practical, 20% theory - focus on hands-on skills and real-world applications.
Limited participants ensure personalized attention and one-on-one mentoring.
Full access to professional simulators and debugging tools for your projects.
What makes this DFT internship impactful for your VLSI career.
Perfect for students and professionals aiming to specialize in chip testing and DFT.
B.Tech / M.Tech Students
ECE, EEE, VLSI, and related disciplines
Fresh Graduates
Interested in starting a DFT-based VLSI career
Working Professionals
Looking to upskill in chip testing and validation
Technical Background
Basic knowledge of digital electronics and Verilog preferred
Achieve the overall objective of implementing a full DFT flow with industry-standard Cadence tools, culminating in a sign-off ready project.
Master the complete Cadence-based DFT Flow: from fault modeling and scan insertion to ATPG generation and pattern simulation.
Insert Full Scan Chains using **Modus DFT**, configure architecture, handle multi-clock domains, and optimize via Chain Reordering and Lock-up Latches.
Generate ATPG patterns for **Stuck-at** and **Transition (Delay)** faults, analyze Fault Coverage, and debug untestable logic (TPI/Redundancy).
Understand the need for compression, implement compression logic (X-masking), and grasp the fundamentals of Memory Built-In Self-Test (MBIST).
Simulate patterns using **Xcelium** (Gate-Level Simulation) with SDF back-annotation, and perform final DFT checks for sign-off.
Hands-on proficiency with Cadence Modus DFT, Xcelium Simulator, and an understanding of interaction with Genus/Innovus for physical aware DFT.
A week-by-week breakdown of the topics covered in our Design for Testability internship.
| Week | Topic | Topic Details / Hands-on |
|---|---|---|
| WEEK 1 | DFT Basics + Cadence Tool Flow | VLSI DFT Basics, Fault Models (SA, Transition, Bridging, Delay), DFT Flow using Cadence Tools (Modus DFT, Xcelium, Genus). Hands-on: Setup environment, run basic DFT checks in Modus. |
| WEEK 2 | Scan Fundamentals | Scan Flops, Scan MUX, Scan Modes & Scan Enable, Controllability & Observability, Scan Design Rules. Hands-on: Replace FF → Scan FF, Insert basic scan chain manually, Run Modus DFT rule checks. |
| WEEK 3 | Scan Insertion Using Cadence Modus | Modus Scan Insertion Flow, Configuring scan parameters, Scan replacement strategies, Handling resets, clocks, gated clocks. Hands-on: Run full scan insertion, Analyze Modus Scan Reports (Chain length, number of chains, lock-up latches). |
| WEEK 4 | Scan Chain Stitching & Optimization | Chain reordering, Multi-clock domain scan handling, Lock-up latch insertion, Physical aware DFT concept. Hands-on: Reorder scan chains, Insert lock-up latches, Verify scan stitching correctness. |
| WEEK 5 | ATPG Basics Using Cadence Modus | ATPG theory, Fault list generation, Stuck-at ATPG, Simulation-ready pattern generation. Hands-on: Run Modus ATPG (Stuck-at), Generate patterns (WGL/STIL), Analyze coverage reports. |
| WEEK 6 | Transition ATPG (Delay Test) | LOS & LOC methods, Timing constraints for ATPG, Handling multi-clock timing, Improving transition coverage. Hands-on: Set transition ATPG constraints, Generate transition delay patterns, Compare SA vs Transition coverage. |
| WEEK 7 | Xcelium Simulation Setup | ATPG pattern simulation basics, Behavioral vs Gate-level simulation, SDF back-annotation, GLS (Gate-level simulation) debugging. Hands-on: Setup Xcelium for ATPG simulations, Apply WGL/STIL patterns, Debug simulation mismatches. |
| WEEK 8 | Test Compression (Cadence Modus) | Need for compression, Compressors/Decompressors, X-masking techniques, Reduction of pattern count. Hands-on: Insert compression logic, Generate compressed patterns, Compare pattern reduction, Run Modus compression reports. |
| WEEK 9 | Fault Coverage Closure & Debug | Debugging untestable faults, Redundant logic analysis, Techniques for coverage improvement, Test-point insertion (TPI). Hands-on: Improve coverage for sample design, Insert observation/control points, Coverage comparison (Pre vs Post TPI). |
| WEEK 10 | Full-Chip DFT Flow (Cadence) | Hierarchical DFT, Black-box handling, Multi-voltage domains, Physical Design + DFT interaction (Genus/Innovus). Hands-on: Integrate multiple modules, Insert scan at top level, Run top-level ATPG, Validate complete DFT flow. |
| WEEK 11 | Final Verification & Sign-off | Modus DFT Checks, ATPG Sign-off, Pattern simulation sign-off, Generating final documentation. Hands-on: Final DFT rule check, Run all ATPG types, Generate final WGL/STIL files, Sign-off coverage & reports. |
| WEEK 12 | Final Project + PPT + Report | Project Options: Full Scan + ATPG + GLS for medium design, Compression-based DFT implementation, DFT coverage improvement project, Multi-clock Scan Design, Hierarchical DFT project. |
Join our specialized DFT internship program and become job-ready in semiconductor testing. Limited seats available!
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