About this course
The Design for Testability (DFT) course by VLSIMinds focuses on the core concepts and practical implementation of VLSI DFT techniques used in semiconductor testing. You’ll gain deep hands-on knowledge of scan insertion, ATPG, fault modeling, and boundary scan using industry-standard EDA tools.
This program bridges the gap between VLSI design and testing, ensuring you understand how to make integrated circuits testable, reliable, and optimized for yield and performance.
What you'll learn
Key Topics
Scan Design
Full scan, partial scan, scan chain balancing and optimization
ATPG & Fault Coverage
Pattern generation, stuck-at faults, transition faults, fault diagnosis
BIST & MBIST
Built-In Self-Test concepts and memory testing techniques
JTAG & IEEE 1149.1
Boundary scan and board-level testing methodologies
Course Curriculum
- Importance of Design for Testability
- Overview of DFT Flow in VLSI
- Full Scan vs Partial Scan
- Scan Chain Insertion & Reordering
- Scan Compression Techniques
- Fault Models and Coverage
- Transition Delay Faults
- Pattern Generation and Optimization
- Logic BIST Architecture
- MBIST & Memory Repair Flow
- Self-Test Controller Implementation
- JTAG Basics
- IEEE 1149.1 and 1500 Protocols
- Board-Level Testing with Boundary Scan
Mr. V. Test
Senior DFT Engineer – VLSIMinds
Experienced VLSI DFT Engineer with 12+ years in semiconductor test design and automation, specializing in ATPG, MBIST, and Boundary Scan methodologies. Worked on advanced nodes (7nm/5nm) and SoC-level testing.
Expertise:
- Scan Design & ATPG
- BIST & MBIST Architecture
- Boundary Scan (JTAG)
- Fault Modeling & Simulation
- Low Power DFT
