About this course
The Design for Testability (DFT) course by VLSIMinds focuses on the core concepts and practical implementation of VLSI DFT techniques used in semiconductor testing. You’ll gain deep hands-on knowledge of scan insertion, ATPG, fault modeling, and boundary scan using industry-standard EDA tools.
This program bridges the gap between VLSI design and testing, ensuring you understand how to make integrated circuits testable, reliable, and optimized for yield and performance.
What you'll learn
Key Topics
Scan Design
Full scan, partial scan, scan chain balancing and optimization
ATPG & Fault Coverage
Pattern generation, stuck-at faults, transition faults, fault diagnosis
BIST & MBIST
Built-In Self-Test concepts and memory testing techniques
JTAG & IEEE 1149.1
Boundary scan and board-level testing methodologies
Course Curriculum
- UNIX/Linux OS overview and file system hierarchy.
- Permissions, basic commands, and GVIM basics.
- Directory management – Hands-on practice.
- Process management and environment variables.
- TCL scripting basics (variables, loops, procedures).
- Tool flow automation scripts.
- Boolean algebra and combinational circuits.
- Timing basics and Verilog combinational modeling.
- RTL coding & simulation.
- Flip-flops, registers, counters, and FSMs.
- Behavioral vs gate-level Verilog.
- FSM design & verification.
- RTL-to-GDSII flow and standard cells.
- Synthesis overview and timing basics.
- RTL synthesis walkthrough.
- Manufacturing defects and fault concepts.
- Yield vs Quality.
- Structural vs Functional testing.
- Scan vs non-scan design and scan cells.
- Scan enable and scan architecture.
- Scan-ready RTL analysis.
- Scan chain planning.
- Clock/reset considerations.
- Tool-based scan insertion – Practical insertion flow.
- Scan DRC checks.
- Chain integrity and scan simulation.
- Debug of violations.
- Test data challenges.
- Compression concepts.
- Decompressor & compactor architecture.
- Compressed scan implementation.
- Control signals.
- Tool-based compression insertion.
- DRCs and coverage comparison.
- Pattern count reduction analysis.
- Memory types and memory fault models.
- Introduction to MBIST.
- MBIST controller, address/data generators.
- March algorithms.
- MBIST insertion.
- Large SoC DFT challenges.
- Hierarchical scan & ATPG.
- Wrappers.
- Structural faults.
- Stuck-at fault model.
- Fault collapsing.
- D-algorithm and path sensitization.
- ATPG tool usage.
- Pattern generation.
- ATPG DRC and fault coverage analysis.
- Untestable fault debugging.
- Transition faults and delay faults.
- Launch/capture mechanisms.
- OCC architecture and clock control.
- At-speed ATPG execution.
- TAP controller and JTAG state machine.
- Instructions.
- JTAG simulation.
- RTL vs Gate-level simulation.
- Functional vs structural simulation.
- Testbench architecture.
- Scan shift/capture simulation.
- Scan chain debug.
- Waveform analysis.
- Applying ATPG patterns.
- Stuck-at and transition fault simulation.
- Coverage validation.
- GLS with SDF and timing checks.
- Reset and X-propagation issues.
- Debugging mismatches.
- Simulation signoff criteria and best practices.
- Project definition.
- RTL/netlist selection.
- DFT strategy.
- Scan & MBIST insertion.
- ATPG generation.
- Gate-level simulation.
- Coverage closure and debug.
- Documentation.
- Final presentation and evaluation.
Mr. V. Test
Senior DFT Engineer – VLSIMinds
Experienced VLSI DFT Engineer with 12+ years in semiconductor test design and automation, specializing in ATPG, MBIST, and Boundary Scan methodologies. Worked on advanced nodes (7nm/5nm) and SoC-level testing.
Expertise:
- Scan Design & ATPG
- BIST & MBIST Architecture
- Boundary Scan (JTAG)
- Fault Modeling & Simulation
- Low Power DFT
