🎯 Objective

To provide hands-on exposure to ASIC design flow focusing on Synthesis and Physical Design using advanced industry-standard EDA tools. Participants will learn how to translate RTL into a physical design layout through a gate-level netlist by optimizing the design for timing, power, and area along with Design for Manufacturability (DFM) rules.

📌 Key Topics Covered

• Module 1: Introduction to ASIC Design Flow
  • Steps in ASIC design flow
  • Synthesis and Physical Design flow
  • Role of Physical Design in yield, reliability, and manufacturability
• Module 2: Synthesis Flow and Optimization Techniques
  • Synthesis flow using advanced EDA tools
  • Analyzing timing, power, and area reports
  • Synthesis optimization techniques to improve timing, power, and area
• Module 3: Physical Design – Floorplanning
  • Custom floorplanning and port placement
  • Role of Physical-only cells for Design for Manufacturability (DFM)
  • Efficient macro placement and power planning
• Module 4: Physical Design – Placement and CTS
  • Standard cell placement controlling techniques
  • Placement optimization flow
  • Efficient building of clock tree and CTS optimization techniques
  • Timing and QoR analysis after placement and CTS
• Module 5: Physical Design – Routing, DRC, and LVS
  • Global and detail routing
  • Analyzing post-route timing issues
  • Analyzing and fixing DRC and LVS violations
• Module 6: Design for Manufacturability
  • Wire widening and redundant via insertion
  • Filler cell insertion
  • Creating final merged GDS

💻 Hands-on Practical Sessions with Industry Standard Tools

• Synthesis flow implementation and report analysis
• Floorplanning, placement, and CTS execution
• Routing and timing closure
• DRC and LVS debugging
• GDS generation and sign-off

👨‍🎓 Target Audience

• VLSI engineers & professionals
• M.Tech/B.Tech students (ECE, VLSI, Embedded Systems)
• Faculty & researchers in semiconductor/analog IC design
• Anyone interested in Synthesis and Physical Design

📅 Duration & Mode

2–5 days (customizable based on depth)
Mode: Offline / Online (Remote Labs)

📜 Outcomes

• Gain a solid foundation in RTL-to-GDSII flow
• Master logic synthesis to convert RTL into a gate-level netlist optimized for timing, area, and power
• Acquire hands-on experience with the Physical Design process flow
• Understand timing and power reports to ensure performance and efficiency
• Gain expertise in analyzing and fixing DRC and LVS issues
• Get practical exposure to leading EDA tools used in the semiconductor industry
• Develop a strong foundation to handle real-world ASIC projects