The Physical Design & Static Timing Analysis (STA) internship gives you hands-on exposure to the backend VLSI design flow. Learn floorplanning, placement, routing, and timing closure techniques used in modern semiconductor design projects. This comprehensive program spans **144 hours** of in-depth training and project work.
Reasons to invest in your VLSI career with us.
Learn from industry veterans with 10+ years of experience at top semiconductor Industries.
80% practical, 20% theory - focus on hands-on skills and real-world applications.
Limited participants ensure personalized attention and one-on-one mentoring.
Full access to professional simulators and debugging tools for your projects.
What makes this Physical Design internship valuable for your backend VLSI career.
This internship is ideal for passionate learners ready to dive into semiconductor design.
B.Tech / M.Tech Students
ECE, EEE, VLSI, and related disciplines
Fresh Graduates
Aspiring to start a career in VLSI design
Working Professionals
Looking to upskill in VLSI design
Programming Background
Basic coding knowledge in HDL/Verilog is beneficial
This **144-hour** program is structured to provide deep technical expertise and professional readiness, combining the entire backend VLSI flow with essential program features.
End-to-end understanding and hands-on implementation of the full physical design flow from netlist to GDSII.
Learn core placement, macro placement, pin assignment, power planning (IR Drop/EM), and congestion management for optimized layouts.
Design, implement, and analyze clock trees (HFNS vs. CTS) for timing closure, power, and useful skew techniques.
Implement global and detailed routing strategies while addressing DRCs, LVS, Open/Shorts, Antenna violations, crosstalk, and IR drop.
Perform comprehensive Setup/Hold analysis and fixing, generate SPEF, and execute signoff using industry-standard tools like Tempus.
Gain hands-on expertise with Cadence Innovus, Synopsys Genus, Tempus, and advanced TCL scripting for design automation and issue fixing.
Work on mini physical design projects simulating actual chip layout and timing closure challenges under expert mentorship.
Mock interviews, technical assessments, project reviews, and job opportunities with partner semiconductor industries to ensure placement readiness.
A week-by-week breakdown of the topics covered in our 144-hour internship.
| Week | Hours | Topic | Topic Details |
|---|---|---|---|
| Week-1 | 12 Hours | Essential Unix and | Basic Unix command. Advance Unix commands (like find, grep, awk etc..). Hands on labs using Linux OS Gvim editor basic commands |
| Week-2 | 12 Hours | Tool Command Language and PD CMOS Basics | TCL: Basic input and output commands. Conditional and loops. List and string operations. TCL file operations. PD CMOS Basics: CMOS Power and delay factors. CMOS Fabrication steps and CMOS layout. FEOL and BEOL layers |
| Week-3 | 12 Hours | ASIC Design flow and STA | ASIC Design Flow: Detail steps in ASIC design flow. Introduction to physical design. STA: Clock and Types of clocks. Clock latency, skew and Uncertainty. Setup and Hold analysis. In to reg and reg to out paths. Example problems. |
| Week-4 | 12 Hours | Synthesis and Physical Design Input files | Synthesis: Inputs for synthesis. Synthesis flow. Logic optimization techniques. Analysis of synthesis reports. Hands on labs using Genus tools. PD Input files: Exploring content of input files. Liberty file, LEF, Tech LEF, Netlist and MCMM file. Import design to Innovus tool. |
| Week-5 | 12 Hours | Floorplanning - PART-1 | Partitioning , differnce between Full chip and blocks level design. Die/core area estimation, Aspect ratio and utilization. IO placement Guidelines. Efficient Macro Placement. |
| Week-6 | 12 Hours | Floorplanning - PART-2 | Physical only cells placement and verification. IR Drop and Electromigration Power planning Structure. Fixing power planning issues. |
| Week-7 | 12 Hours | Exploring Innovus tool for Automation. | Legacy and Stylus mode. Objects, attributes and attribute values. dbGet and dbSet Commands. Hands on to write TCL automated programs. |
| Week-8 | 12 Hours | Placement | Pre-placement checks. Application options for placement. Placement constraints. Timing-driven and Congestion driven placement. Placement optimization techniques. Congestion analysis & fixes. Analysing timing DRVs and timing. |
| Week-9 | 12 Hours | Clock Tree Synthesis | HFNS vs CTS. CTS constraints & exceptions. Non-default routing rules. CTS specification file. Analysis of latency, skew and Pulse width after CTS. Analysis of Setup and Hold violations. Useful skew technique. |
| Week-10 | 12 Hours | Routing | Global vs Detailed routing. Routing constraints. Cross talk delay and cross talk noise. Analyzing and Fixing DRCs. Analyzing and Fixing Open and shorts. Fixing Antenna violations. |
| Week-11 | 12 Hours | TCL Automation in Analysing and fix Issues | TCL automated scripts. To get route lengths. To Fix DRV violations. To Analyze and filter timing reports. To fix timing violation. To grep values from PD reports. |
| Week-12 | 12 Hours | Timings Signoff | SPEF Extraction. Inputs to Tempus tool. DRV analysis. Setup and Hold analysis and fixing. Generating ECO file. Implementing ECO in Innovus too |
| Total | 144 hours of content | ||
Enroll in our internship program and become a backend VLSI design professional. Limited seats available!
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