🎯 Objective

To provide hands-on exposure to analog custom IC layout design concepts, methodologies, and industry practices using foundry-provided PDKs and industry-standard EDA tools. Participants will learn how to translate schematics into optimized physical layouts, adhering to DRC, LVS, and parasitic-aware design practices essential for first-time-right silicon.

📌 Key Topics Covered

• Module 1: Introduction to Analog Custom Layout
  • Overview of analog IC design flow
  • Importance of layout in analog/mixed-signal performance
  • PDKs and technology files overview
  • Role of layout in yield, reliability, and manufacturability
• Module 2: MOSFET Layout Fundamentals
  • Transistor layout styles (common-centroid, inter-digitated, multi-finger)
  • Well, diffusion, and poly considerations
  • Device matching principles and symmetry in layout
  • Hands-on: Basic MOS layout using Industry standard tools
• Module 3: Passive Components & Layout Techniques
  • Resistor and capacitor layout strategies
  • Guard rings, shielding, and isolation techniques
  • Parasitic reduction in R, C, and interconnects
  • Hands-on: Passive device layout & verification
• Module 4: Analog Layout Best Practices
  • Current mirror layout techniques
  • Differential pair layout and matching strategies
  • Layout for low-noise and high-speed circuits
  • Hands-on: Differential amplifier layout
• Module 5: Parasitic Awareness & Verification
  • Parasitic capacitance and resistance in analog layouts
  • LPE (Layout Parasitic Extraction) basics
  • DRC, LVS, and ERC checks in analog flows
  • Hands-on: LVS debugging and parasitic extraction
• Module 6: Advanced Analog Layout Topics
  • Common-centroid & inter-digitated structures
  • Layout techniques for op-amps, comparators, and current references
  • Floorplanning for mixed-signal designs
  • Industry case studies and best practices

💻 Hands-on Practical Sessions

• MOSFET, resistor, capacitor layout & verification
• Current mirror and differential pair layout
• DRC/LVS checks and debugging
• Parasitic extraction and performance impact analysis

👨‍🎓 Target Audience

• VLSI engineers & professionals
• M.Tech/B.Tech students (ECE, VLSI, Embedded Systems)
• Faculty & researchers in semiconductor/analog IC design
• Anyone interested in analog custom layout design

📅 Duration & Mode

2–5 days (customizable based on depth)
Mode: Offline / Online (Remote Labs)

📜 Outcomes

• Understand analog layout fundamentals and best practices
• Be able to design and verify MOS, passive, and analog building blocks layouts
• Gain expertise in DRC, LVS, and parasitic-aware design flow
• Be industry-ready for Analog/Mixed-Signal Layout Engineering roles