About this course
Physical Design is a crucial part of the VLSI design cycle, transforming the gate-level netlist into the final layout (GDSII) ready for fabrication. This comprehensive course provides hands-on expertise in industry-standard tools and techniques for high-performance, low-power chip design.
You will learn how to handle complex challenges like timing closure, signal integrity, and design rule checking (DRC/LVS). A strong foundation in Static Timing Analysis (STA) is also integrated to ensure timing sign-off readiness.
What you'll learn
Key Topics
Physical Design
Floorplanning, placement, routing, and layout optimization
STA Concepts
Setup/Hold time, clock skew, and timing constraints
Tools & EDA
Industry-standard tools like Cadence, Synopsys, Mentor
Sign-off Methods
DRC, LVS, and design verification techniques
Course Curriculum
- Overview of VLSI Backend Flow
- Input Files (Netlist, LEF, DEF, SDC)
- Design Files and Specifications
- Die and Core Area Definition
- Power Rail and Ring Generation
- Macro Placement Guidelines
- Standard Cell Placement
- Pre-CTS Optimization
- High Fanout Net Synthesis
- Clock Tree Generation & Tuning
- Global and Detailed Routing
- Post-Route Optimization
- STA Fundamentals & Timing Concepts
- Setup and Hold Time Analysis
- Clock Skew and Jitter
- Timing Paths and Critical Path Analysis
- Library Setup & Operating Conditions
- STA Tool Usage and Sign-off
- Design Rule Checking (DRC)
- Layout Versus Schematic (LVS)
- Final Sign-off Procedures
Mr. V. LSI
Principal Physical Design Engineer
Industry veteran with 15+ years of experience in VLSI Physical Design and Static Timing Analysis at leading semiconductor Industries. Specializes in advanced process nodes and high-performance chip implementation.
Expertise:
- Physical Design & Backend
- Static Timing Analysis
- Advanced Process Nodes (7nm, 5nm)
- EDA Tools & Design Automation
- Timing Closure & Optimization
