About this course
Physical Design is a crucial part of the VLSI design cycle, transforming the gate-level netlist into the final layout (GDSII) ready for fabrication. This comprehensive course provides hands-on expertise in industry-standard tools and techniques for high-performance, low-power chip design.
You will learn how to handle complex challenges like timing closure, signal integrity, and design rule checking (DRC/LVS). A strong foundation in Static Timing Analysis (STA) is also integrated to ensure timing sign-off readiness.
What you'll learn
Key Topics
Physical Design
Floorplanning, placement, routing, and layout optimization
STA Concepts
Setup/Hold time, clock skew, and timing constraints
Tools & EDA
Industry-standard tools like Cadence, Synopsys, Mentor
Sign-off Methods
DRC, LVS, and design verification techniques
Course Curriculum
- Gvim Commands: Major file editing shortcut commands.
- Unix Commands: UNIX/Linux OS overview, file system hierarchy, permissions handling, Unix basic commands, directory management.
- Advanced Linux: Commands like grep, sed and awk etc.
- Basic input and output commands.
- Conditional statements and loops.
- List and string operations.
- TCL file operations.
- Examples Programs - Hands on project.
- TCL regular expression.
- TCL procedure.
- TCL arrays and dictionaries.
- Examples Programs - Hands on project.
- Boolean algebra and combinational circuits.
- Timing basics.
- Verilog combinational modelling – RTL coding & simulation.
- Flip-flops, registers, counters, and FSMs.
- Behavioural vs gate-level Verilog.
- FSM design & verification.
- Types of Semiconductors and BJT vs MOSFETs.
- MOSFET classification and regions of operations.
- CMOS operation and CMOS circuits.
- IC fabrication steps and CMOS layout.
- FEOL and BEOL layers.
- Packaging, wire bond and flip chip design.
- ASIC design flow and Timing basics.
- Wire delay and Cell delay (and dependent parameters).
- CMOS power classification and dependent parameters.
- Clock and Types of clocks.
- Clock latency, skew and Uncertainty.
- Setup and Hold analysis.
- In to reg and reg to out paths.
- Example problems.
- OCV - Derates and types of Derates.
- PVT conditions and RC corners.
- Modes, Corners and Scenarios.
- SDC constraints and MCMM file.
- STA on asynchronous signals.
- Inputs for synthesis and Synthesis flow.
- Hierarchical and flat synthesis.
- Logic optimization techniques.
- Generating SDC file.
- Generating UPF file for lower power design.
- Physical Aware synthesis.
- PD environmental setup.
- Exploring PD input files.
- Import design and different design formats.
- Sanity checks on input files.
- Legacy and Stylus mode.
- Objects, attributes and attribute values.
- Exploring dbGet and dbSet Commands.
- TCL automated programs using dbGet - Hands on.
- Top v/s Block level physical design.
- Partitioning, Sub system and blocks.
- Creating Core area and Die area.
- Custom Port placement.
- Macro placement guidelines and Efficient Macro placement.
- Physical only cells placement.
- Low power design and UPF.
- Creating Voltage areas for different power domains.
- Inserting and planning power switch placement.
- Robust power planning.
- Fixing Power issues to meet IR drop and DRCs.
- Pre-Placement checks and Placement steps.
- Scan chain reordering.
- TIE cell insertion.
- Types of placements and placement optimization.
- Blockages and types of blockages.
- Different types of placement Bounds.
- Controlling Placement density.
- Creating balanced Buffer trees for High Fanout Net.
- Congestion and time driven placement.
- Analysing and fixing Congestion.
- Analysing and fixing timing DRVs (max cap, max trans, max fanout).
- Analysing and fixing timing Issues.
- Path grouping.
- TCL automation for timing analysis and fixing.
- Pre-CTS checks.
- HFNS v/s Clock tree synthesis.
- Clock skew, latency and jitter.
- CTS steps and types of CTS.
- Clock nets shielding.
- CTS buffers and inverters for clock trees.
- Target latency and Target skew.
- Non-default routing rules.
- Clock tree exceptions.
- Don’t touch attributes on clock tree.
- Analysing insertion delay and skew.
- Analysing and fixing pulse width violations.
- Analysing Clock path DRVs (max cap, max trans, max fanout).
- Analysing and fixing Timing violations (Setup and Hold).
- Useful skew method.
- Max and Min Analysis and subsequent Optimization.
- CTS Optimization across different modes and PVT corners.
- Pre-route checks.
- Global v/s detail routing.
- Track assignment.
- Routing techniques for critical and special nets.
- Cross talk noise and cross talk delay.
- Fixing cross talk noise and delay.
- Antenna violation and Electromigration checks.
- Analysing and Fixing DRC, LVS and ERC issues.
- Antenna violation fixing (Metal jogging and diode insertion).
- Post route DRVs and Timing analysis.
- Add buffer on routes and Cross talk delay analysis.
- Antenna Rules and Fixes.
- Critical Area Analysis.
- Wire Spreading and widening.
- Filler Cell Insertion.
- Dummy Metal Fill.
- Understand the input files for SPEF extraction.
- SPEF extraction for different RC corners.
- Flat and Hierarchical extraction.
- Exploring the content of SPEF file.
- Understand input files for timing signoff.
- Creating sessions for setup and hold scenarios.
- Analysing and Fixing setup and hold timing.
- Analysing and fixing DRVs, Crosstalk noise and delay.
- TCL automated scripts to get route lengths.
- To Fix DRV violations and analyze/filter timing reports.
- To fix timing violation and grep values from PD reports.
- Metal/Base level DRC checks, LVS, and Antenna fixing.
- ERC, Density & CMP Checks.
- Static/Dynamic IR drop analysis (Vectored and Vectorless).
- Sources of IR Drop and Fixing IR Drop Violations.
Mr. V. LSI
Principal Physical Design Engineer
Industry veteran with 15+ years of experience in VLSI Physical Design and Static Timing Analysis at leading semiconductor Industries. Specializes in advanced process nodes and high-performance chip implementation.
Expertise:
- Physical Design & Backend
- Static Timing Analysis
- Advanced Process Nodes (7nm, 5nm)
- EDA Tools & Design Automation
- Timing Closure & Optimization
