Objective

To provide hands-on exposure to analog custom IC layout design concepts, methodologies, and industry practices using foundry-provided PDKs and industry-standard EDA tools. Participants will learn how to translate schematics into optimized physical layouts, adhering to DRC, LVS, and parasitic-aware design practices essential for first-time-right silicon.

Key Topics Covered

• Module 1: Introduction to Analog Custom Layout
  • Overview of analog IC design flow
  • Importance of layout in analog/mixed-signal performance
  • PDKs and technology files overview
  • Role of layout in yield, reliability, and manufacturability
• Module 2: MOSFET Layout Fundamentals
  • Basic MOSFET layout styles
  • Device sizing and matching
  • Common-centroid and interdigitated structures
  • Guard rings and isolation techniques
• Module 3: Passive Devices & Interconnects
  • Resistor and capacitor layout strategies
  • Metal routing and multi-layer interconnects
  • Minimizing parasitics for optimal performance
  • Routing rules and design guidelines
• Module 4: Verification & DRC/LVS
  • Design rule check (DRC)
  • Layout versus schematic (LVS)
  • Electrical rule check (ERC)
  • Parasitic extraction and timing verification
• Module 5: Full Custom Layout Project
  • Hands-on project integrating all modules
  • Optimization for performance, power, and area
  • Final verification and sign-off process