About this course
This course provides a complete understanding of RTL Design and Functional Verification in the VLSI front-end flow. You’ll learn to write synthesizable RTL using Verilog and SystemVerilog, and verify it using industry-standard UVM methodologies.
By the end, you’ll gain practical exposure to building testbenches, simulating RTL designs, and debugging functional issues in complex digital systems.
What you'll learn
Key Topics
RTL Design
Digital logic, finite state machines, and synthesizable design.
Verification
Testbench development, constrained random testing, coverage.
UVM
Reusable, scalable, and modular verification framework.
Simulation Tools
Industry standard tools like ModelSim, VCS, and QuestaSim.
Course Curriculum
- UNIX/Linux OS overview, file system hierarchy, and permissions.
- Basic commands, GVIM basics, and directory management.
- Hands-on practice sessions.
- Process management and environment variables.
- TCL scripting basics (variables, loops, procedures).
- Tool flow automation scripts.
- Boolean algebra, combinational circuits, and timing basics.
- Verilog combinational modeling – RTL coding & simulation.
- Flip-flops, registers, counters, and FSMs.
- Behavioral vs gate-level Verilog.
- FSM design & verification.
- ASIC flow, Hardware Description & Verification languages.
- Introduction of Verilog concepts.
- Hardware Data types, integer data types, and register data types.
- Module ports, Scalar & vectors.
- Arrays and Array operations.
- Arithmetic, Logical, Equality, Concatenation, and Replication.
- Bitwise and Shift operators.
- Behavioral, Structural, and Data flow level for different designs.
- DUT – TB instantiations.
- Tasks & Functions, Blocking & Non-Blocking Assignments.
- Fork-join, if, else-if, case, for, and while loops.
- Significance of $display, $monitor, and timescale.
- Parameters, `define, `include, and $value$plusargs.
- Clock Generation techniques.
- Project: Design & Verification of Single Port RAM.
- Modularity & Re-usability concepts.
- Pre-defined methods, data types, and operators.
- System Verilog Functions.
- Integer, void, and String data types.
- User-defined data types (typedef, enum, struct, union).
- Packed & unpacked arrays, and static arrays.
- Whole array operations, dynamic arrays, queues, and Associative arrays.
- Classes, Objects, Properties, and Methods.
- Handle Assignments and the new() constructor.
- Shallow copy vs Deep copy.
- Inheritance and Polymorphism.
- Data Encapsulation.
- Static properties & methods, and scope-resolution operator.
- Randomization methods and constraint types.
- Pattern generation using constraints.
- Inter-process synchronization: Mailboxes, semaphores, and events.
- DPI, interface, clocking blocks, and modports.
- Virtual interfaces and drivers.
- Monitor, Scoreboard, Agent, and Top module.
- Coverage collector and concurrent Assertions.
- Properties and Verification IP.
- Project: Verification of Asynchronous FIFO.
- Evolution of UVM and UVM Base classes.
- TB Topology and Factory basics.
- Object methods.
- Reporting mechanism: Severity and verbosity.
- UVM Phases, objections, and running a test case.
- TLM ports and TLM FIFO.
- Analysis Ports and Analysis FIFO.
- Config_db and resource_db.
- Development of sequence, driver, monitor, scoreboard, and subscriber.
- Sequence library and test library.
- Sequence-sequencer-driver communication.
- Virtual sequences & virtual sequencers.
- uvm_macros usage.
- Sequence start_item & finish_item.
- Starting sequence & UVM revision.
- Project: Memory & Asynchronous FIFO TB Development.
Mr. R. Logic
Senior RTL & Verification Engineer
Industry professional with 12+ years of experience in RTL Design, SystemVerilog, and UVM Verification across top semiconductor Industries. Expert in building reusable verification environments for SoCs and IPs.
Expertise:
- Verilog & SystemVerilog
- UVM Verification
- Functional & Assertion-based Verification
- Simulation & Debug
- Testbench Architecture
