About this course
This course provides a complete understanding of RTL Design and Functional Verification in the VLSI front-end flow. You’ll learn to write synthesizable RTL using Verilog and SystemVerilog, and verify it using industry-standard UVM methodologies.
By the end, you’ll gain practical exposure to building testbenches, simulating RTL designs, and debugging functional issues in complex digital systems.
What you'll learn
Key Topics
RTL Design
Digital logic, finite state machines, and synthesizable design.
Verification
Testbench development, constrained random testing, coverage.
UVM
Reusable, scalable, and modular verification framework.
Simulation Tools
Industry standard tools like ModelSim, VCS, and QuestaSim.
Course Curriculum
- Overview of VLSI Front-end Design
- Design Entry and Simulation Setup
- Data types, Operators, and Procedural Blocks
- Sequential and Combinational Logic
- FSM Implementation
- Testbench Architecture
- Assertions and Coverage
- Constrained Random Verification
- UVM Components (Driver, Monitor, Agent)
- Sequences and Scoreboards
- Factory and Configuration
- UVM Environment Integration
Mr. R. Logic
Senior RTL & Verification Engineer
Industry professional with 12+ years of experience in RTL Design, SystemVerilog, and UVM Verification across top semiconductor Industries. Expert in building reusable verification environments for SoCs and IPs.
Expertise:
- Verilog & SystemVerilog
- UVM Verification
- Functional & Assertion-based Verification
- Simulation & Debug
- Testbench Architecture
