Gain comprehensive exposure to digital design methodologies and verification techniques through practical projects and structured training.

• Develop RTL modules using Verilog/SystemVerilog
• Create and simulate testbenches for functional verification
• Analyze design behavior and debug issues
• Implement coverage-driven verification techniques
• Hands-on projects with industry-standard EDA tools

Learn to integrate test features into digital circuits ensuring high-quality manufacturing and reliable operation.

• Scan chain design & analysis for fault detection
• Boundary scan (JTAG) and built-in self-test (BIST)
• ATPG & fault coverage analysis
• Test pattern generation and debugging
• Hands-on projects using industry-standard DFT tools

Transform RTL designs into manufacturable silicon using advanced physical design flow and timing analysis techniques.

• Floorplanning, placement, and routing of designs
• Clock tree synthesis (CTS) and timing closure
• DRC/LVS verification and signal integrity checks
• Static Timing Analysis (STA) and power optimization
• Hands-on experience with Innovus, IC Compiler, and PrimeTime

Hands-on training in transistor-level analog layout, parasitic extraction, and precision design techniques for analog/mixed-signal circuits.

• Transistor-level layout and matching techniques
• DRC & LVS verification and layout validation
• Parasitic extraction for performance optimization
• Analog floorplanning and signal integrity management
• Hands-on experience with Cadence Virtuoso and Assura tools