The RTL Design & Verification internship is a project-based, **12-week, 100+ hours** program structured to provide comprehensive exposure to digital design methodologies and verification techniques. You will implement a complete functional **SoC Subsystem** using real-world blocks, leveraging Verilog/SystemVerilog and industry planning tools.
Reasons to invest in your VLSI career with us.
Learn from industry veterans with 10+ years of experience at top semiconductor Industries.
80% practical, 20% theory - focus on hands-on skills and real-world applications.
Limited participants ensure personalized attention and one-on-one mentoring.
Full access to professional simulators and debugging tools for your projects.
What makes this internship unique and valuable for your career.
This internship is ideal for passionate learners ready to dive into semiconductor design.
B.Tech / M.Tech Students
ECE, EEE, VLSI, and related disciplines
Fresh Graduates
Aspiring to start a career in VLSI design
Working Professionals
Looking to upskill in VLSI design
Programming Background
Basic coding knowledge in HDL/Verilog is beneficial
This project-centric program guarantees hands-on mastery of core digital design and RTL development concepts for job readiness.
Master digital design fundamentals, Verilog/SystemVerilog coding, and RTL architecture thinking for synthesizable logic (FSMs, Counters, Sequential/Combinational logic).
Implement and integrate complex SoC macros like **Counter, Comparator, Power/Clock Control, and Memory** into one working functional subsystem.
Gain practical experience in implementing and converting data between industry-standard communication protocols like **UART, SPI, and I2C**.
Learn fundamental verification concepts, including SystemVerilog structures, Interfaces, and Assertions for efficient testbench creation.
Implement and manage complex power modes (Sleep/Deep Sleep) and clock distribution using dedicated **Power Control** and **Clock Scaler/Controller** blocks.
Learn to use real-world planning tools (like Freeplane) for requirement tracking, block diagram creation, and managing the entire project flow.
The entire internship is built around developing a complete, functional SoC subsystem, integrating all concepts into a final project.
32-bit up-counter (up to ≈ 136 years) with internal registers for time (seconds to years). Features include configurable MAX_COUNT register and Overflow Interrupt generation.
Receives count value from COUNTER, compares it against a stored target value (Compare Register), and generates a Match Interrupt.
Accepts and prioritizes interrupts from Counter (Overflow), Comparator (Match), and External Wakeup Pin. Supports No Detect / Rising Edge / Falling Edge modes.
Manages SoC power modes (sleep & deep sleep). Can shut off power to peripherals. Configurable wakeup sources (Overflow, Match, Wakeup Pin).
**Scaler:** Divides/multiplies input clock frequency with programmable ratios. **Controller:** Distributes clock, enabling it only when a block requests for power/performance optimization.
Implement a real-world protocol converter (UART ↔ SPI). Demonstrates FSM design, data buffering, and timing synchronization between protocols.
The program includes design basics for: **Always-ON Block** (minimal logic for wakeup), **MEMORY Block** (stores configuration/runtime data), **SPI Protocol**, **UART Protocol**, and **I2C Protocol**.
**Final Integration:** All implemented modules (Counter, Comparator, Power, Clock, Communication, Memory, etc.) are connected and mapped to form a single, working SoC Subsystem.
Start your journey towards becoming a semiconductor design expert today. Limited seats available for this batch!
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