🎯 Objective

To provide hands-on exposure to the DFT concepts, methodologies, and implementation techniques in the VLSI design flow using industry-standard EDA tools. Participants will learn how to integrate testability features into designs, ensuring high fault coverage and faster time-to-market.

📌 Key Topics Covered

• Module 1: Introduction to DFT
  • Importance of testability in VLSI
  • Fault models: Stuck-at, transition, bridging, delay faults
  • Role of DFT in ASIC/SoC design flow
• Module 2: Scan Design Techniques
  • Scan chain basics & architecture
  • Insertion of scan flip-flops
  • Scan planning and optimization
  • Hands-on: Scan insertion using industry standard tools
• Module 3: ATPG (Automatic Test Pattern Generation)
  • Basics of ATPG & fault simulation
  • Deterministic vs. Pseudo-random patterns
  • Stuck-at & transition fault ATPG
  • Hands-on: ATPG generation & coverage analysis
• Module 4: Memory Test (MBIST)
  • Basics of MBIST architecture
  • Test algorithms (March tests, checkerboard, etc.)
  • Hands-on: MBIST insertion & simulation using industry standard tools
• Module 5: Boundary Scan (JTAG – IEEE 1149.1)
  • Concept of boundary scan & TAP controller
  • Board-level testing using JTAG
  • Hands-on: Implementing boundary scan
• Module 6: DFT Sign-off & Industry Practices
  • Fault coverage analysis
  • Power-aware test techniques
  • Debugging and failure diagnosis
  • Industry case studies

💻 Hands-on Practical Sessions with Industry Standard Tools

• Scan insertion & verification
• ATPG pattern generation & simulation
• MBIST architecture integration
• Boundary scan implementation
• Coverage analysis & optimization

👨‍🎓 Target Audience

• VLSI engineers & professionals
• M.Tech/B.Tech students (ECE, VLSI, Embedded Systems)
• Faculty & researchers in semiconductor design
• Anyone interested in DFT and VLSI design

📅 Duration & Mode

2–5 days (customizable based on depth)
Mode: Offline / Online (Remote Labs)

📜 Outcomes

• Understand DFT principles in modern ASIC/SoC design
• Be able to implement scan chains, ATPG, MBIST, and JTAG
• Gain hands-on experience with Industry Standard DFT tools
• Be industry-ready for DFT engineering roles