The Custom Analog Layout Design internship provides intensive hands-on experience in designing and optimizing analog and mixed-signal layouts. Learn transistor-level layout, parasitic extraction, and matching techniques critical for precision analog ICs. This is a comprehensive **12-Week, 100+ Hours** program focused on sign-off ready analog IP design.
Reasons to invest in your VLSI career with us.
Learn from industry veterans with 10+ years of experience at top semiconductor Industries.
80% practical, 20% theory - focus on hands-on skills and real-world applications.
Limited participants ensure personalized attention and one-on-one mentoring.
Full access to professional simulators and debugging tools for your projects.
Why this Analog Layout internship is a great investment for your career.
This internship is ideal for passionate learners ready to dive into semiconductor design.
B.Tech / M.Tech Students
ECE, EEE, VLSI, and related disciplines
Fresh Graduates
Aspiring to start a career in VLSI design
Working Professionals
Looking to upskill in VLSI design
Programming Background
Basic coding knowledge in HDL/Verilog is beneficial
This 12-week program is designed to deliver industry-ready expertise for custom analog layout roles, focusing on sign-off skills.
Master the complete flow: Schematic → Layout → DRC → LVS → PEX → Simulation for sign-off ready circuits.
Create layouts for basic devices, multi-finger MOS, current mirrors, differential pairs, poly resistors, and MOS/MOM capacitors with a focus on matching and symmetry.
Learn hierarchical layout, block-level floorplanning, power routing, guarding, shielding, and parasitic-aware routing.
Perform comprehensive verification using industry tools (Assura/PVS/Quantus) to ensure fabrication readiness.
Develop skills to optimize layout for reduced parasitics, improved matching, and performance (e.g., gain, offset, speed).
Complete a full analog IP layout project (Op-Amp/Comparator) using Cadence Virtuoso/Custom Compiler under expert mentorship.
A week-by-week breakdown of the topics covered in our Custom Analog Layout Design internship, culminating in a sign-off ready project.
| Week | Topic | Topic Details / Hands-on / Mini-Project |
|---|---|---|
| WEEK 1 | Introduction & Foundations | Overview: Schematic → Layout → DRC → LVS → PEX → Simulation. MOS basics, W/L sizing, Tool environment (layers, grids, tech file). Mini-Project: Inverter layout, Run DRC + LVS. |
| WEEK 2 | Basic Devices & Layout Rules | Transistor orientation rules, Contacts, vias, enclosure rules, Design rule categories (spacing, width, density). Hands-on: Build multi-finger MOS, create transistor arrays. Mini-Project: Multi-finger NMOS/PMOS layout. |
| WEEK 3 | Analog Building Blocks | Current mirrors, Differential pairs, Cascode devices, Matching & symmetry rules. Hands-on: Current mirror layout, Differential pair layout, Interdigitated / common-centroid patterns. |
| WEEK 4 | Passive Components Layout | Poly resistors / Metal resistors, Capacitors (MOSCAP, MOMCAP), Guard rings, shielding, Dummy structures. Hands-on: Poly resistor, MOM capacitor layout, Add guard rings, Parasitic-aware routing. |
| WEEK 5 | Sub-block Layout Practice | Basic analog blocks: Current biasing networks, Simple OTA, Comparator basics. Hands-on: Create bias block layout, Comparator pre-layout, Start hierarchical layout mindset. |
| WEEK 6 | Floorplanning & Hierarchical Layout | Block-level floorplanning, Placement strategy, Routing methodology, Power routing, shielding strategy. Hands-on: Floorplan analog block, Place matched groups, Routing analog-critical paths. |
| WEEK 7 | Full Block Layout (Part 1) | Start full chosen analog block (Two-stage Op-Amp / OTA / Comparator / LDO sub-block). Hands-on: Transistor placement, Matching and symmetry enforcement, Initial routing, DRC clean-up. |
| WEEK 8 | Full Block Layout (Part 2) | Completing routing, Clock/signal routing rules, Power integrity considerations, Area optimization techniques. Hands-on: Finish routing, Metal density & fill rules, EM/IR overview. |
| WEEK 9 | Parasitic Extraction (PEX) | StarRC / Quantus extraction, Understanding R & C parasitics, How parasitics affect amplifier performance. Hands-on: Extract layout (PEX), Import to simulator, Compare Pre-layout vs Post-layout performance. |
| WEEK 10 | Layout Optimization | Common reasons for mismatch, Reducing parasitic capacitance, Minimizing routing resistance, Improving common-mode rejection (CMRR). Hands-on: Optimize layout, Verify improvement in simulation, Run DRC/LVS/PEX again. |
| WEEK 11 | Final Integration & Sign-off | Final checks: DRC, LVS, PEX, ERC, Antenna rules, Density checks. Preparing GDS for tape-out. Hands-on: Generate GDS, Full sign-off verification, Prepare documentation. |
| WEEK 12 | Final Project + PPT + Report | Final Deliverables: Schematic, Device sizing document, Complete layout, DRC/LVS clean, Post-layout simulation, Final GDS, Final PPT + Report, Internship Completion Certificate. |
Join our internship to become a professional in analog/mixed-signal layout design. Limited seats available!
Apply Now